1. Technical Field of the Invention
This invention relates generally to data communications and more particularly to data recovery within such communication systems.
2. Description of Related Art
In general, broadband communications are high-speed (e.g., greater than 45 megabits-per-second) data transmissions within a wide area network (WAN). Typically, broadband communication systems are fiber optic in nature. For example, many broadband networks include fiber optic interfaces that are constructed in accordance with SONET (Synchronous Optical NETwork). As is known, SONET is an optical interface standard that allows internetworking of transmission products from multiple vendors and prescribed transmission rates from 51.84 megabits-per-second to over 10 gigabits-per-second.
As is further known, data transmissions via fiber optic links are serial streams of data, but within a network component (e.g., switch, relay, bridge, gateway, et cetera) the data is processed in parallel. As such, each network component includes a serial-deserial transceiver (i.e., transmitter and receiver). In general, the transmitter converts parallel data into serial data and sources the serial data onto a fiber optic link. A receiver receives serial data via a fiber optic link and converts it back into parallel data.
Needless to say, a critical function of the receiver is to accurately sample the received serial data to be able to produce the parallel data. While the data rates for fiber optic transmissions are specified, hence the required clock signals are also specified, the clocks of fiber optic transceivers are not synchronized. Thus, the phase and/or frequency of the transmitter sourcing the received serial data may not align with the clock signal of the receiver. Such a misalignment, if uncorrected, produce errors in the resulting parallel data. To correct the misalignment, receivers include a data and clock recovery circuit, which may include a phase locked loop (PLL) architecture or a delay locked loop (DLL) architecture.
DLL's are known to include a phase detector, loop filter and a phase interpolator. As is known, the phase detector determines a phase difference between the rate of the received serial data and the clock of the receiver. If a difference exists, the phase detector provides a signal to the loop filter, which produces a control signal therefrom. The phase interpolator processes the control signal to adjust the phase of the receiver's clock.
FIG. 1 is a schematic block diagram of a phase interpolator that is widely used in DLL's of various types of digital communication systems, including fiber optic networks. As shown, the phase interpolator employs several fixed clock phases (e.g., 0°, 90°, 180°, 270°) and creates a phase clock, which is between 0° and 360° with certain fixed steps. For example, the phase interpolator of FIG. 1 can produce 16 phases of a reference clock with steps corresponding to 360° divided by 16. The selection of a particular phase is based on the enablement of switches D0-D15.
As shown, each switch controls a current source that when enabled couples the current source to the output (e.g., the recovered clock signal) via a transistor. For example, if the desired phasing of the recovered clock signal is 0°, switches D0-D3 are enabled and the remaining switches are disabled. For a phase shift of 360° divided by 16, switches D1-D4 are enabled while D0 and D5-D15 are disabled. Accordingly, each phase step is achieved by enabling various combinations of the switches.
An issue with such a phase interpolator is that ¾ths of the current sources are shut-off and only ¼th of the current sources are used to establish the desired phase. In addition, when a phase change occurs, some current sources will be shut-off and some current sources will be turned on, which creates a glitch at the output thereby reducing the integrity of the recovered clock signal. Further, since all current sources have to be well matched to improve accuracy of the output phases, large sized transistors are used, which results in large die area for the phase interpolator. Accordingly, the die area of the corresponding DLL increases, which increases the overall cost and power consumption for data recovery circuits.
Therefore, a need exists for a more efficient data and clock recovery circuit for use in digital communication systems.